A Practical Introduction to PSL (Integrated Circuits and Systems) 2006th Edition by Cindy Eisner , Dana Fisman

Functional verification is hard. Period. No disagreement here. But why is this so? Consider today’s design flow: much of it is more or less automated, from RTL to netlist to layout to silicon. But all this automation depends upon having correct RTL input to start with, and there is little or no automation to help with RTL creation. It is hard enough for a designer to decide what RTL model he wants to build, and then to describe that RTL model correctly in a hardware description language. It is even more difficult for a verification engineer, who can’t read the designer’s mind, to verify that what the designer created not only represents the RTL model he had conceived, but also that the RTL model is an appropriate one for the problem at hand. What makes RTL modeling and verification difficult is concurrency. It is easy to teach an engineer how to write procedural code that conforms to the synthesizable subset of a hardware description language. What is hard is understanding how the engineer’s procedural code interacts with other components in the design over time. In fact, until recently we lacked effective languages to describe concurrent behaviors. The IEEE 1850 Property Specification Language (PSL) is a language for the formal specification of concurrent systems. The language is particularly applicable for writing assertions about hardware designs. PSL supports multiple verification paradigms – including formal analysis, simulation, and acceleration/emulation.